Welcome to my webpage!
Currently, I am working as a Principal Software Engineer at Cadence Design Systems. I develop the power optimization software for the Innovus Implementation System.
I earned my PhD from the BRIDGE Lab of Utah State University, working under the supervision of Dr. Koushik Chakraborty and Dr. Sanghamitra Roy. My general areas of research were Computer Architecture and VLSI. Specifically, I worked on the reliability of Network-on-Chips, near-threshold circuit-architecture co-design for GPUs and TPUs, and hardware security for near-threshold computing.
Prior to joining the PhD program, I worked at Mirafra Technologies, India, as an R&D Engineer - II, for 3 years (2011 - 2014). At Mirafra, I was an EDA software developer for The Xilinx Vivado™ Design Suite. Broadly, I was involved in reducing the static and dynamic power for the largest FPGA devices of the industry. I also worked at Xilinx Inc., San Jose, as a summer intern in 2016, and was involved in developing the FPGA logic optimization and physical synthesis tools. I have also interned at Intel Corp., San Jose, in the summer of 2018, where I developed the physical synthesis tool for Intel FPGAs.
I received my Bachelors of Engineering degree (with First Class Honors) in Instrumentation and Electronics, from Jadavpur University, India in 2011. My Bachelor's thesis involves characterization of negative temperature coefficient thermistors.
Specialties: EDA, VLSI, FPGA, Computer Architecture, Network-on-Chip, Near-Threshold Computing.